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description agilents INA-34063 is a silicon rfic amplifier that offers excellent gain and output power for applications to 3.0 ghz. packaged in an ultraminiature sot-363 package, it requires half of the board space of a sot-143 package. with its wide bandwidth and high linearity, the INA-34063 is suitable as a driver amplifier for various applications. the INA-34063 also features high reverse isolation, making it an excellent candidate for lo buffer applications. the INA-34063 is fabricated using agilents 30 ghz C fmax, isosat? silicon-bipolar process that uses nitride, self-alignment, submicrometer lithography, trench isolation, ion implantation, and polyimide intermetal dielec- tric and scratch protection to achieve superior performance, uniformity and reliability. 3.0 ghz medium power silicon rfic amplifier technical data INA-34063 surface mount sot-363 (sc-70) package pin connections and package marking simplified schematic output & v d gnd 1 34 gnd 2 gnd 1 input 1 2 3 6 5 4v d note: package marking provides orientation and identification. features ? +8 dbm p 1 db at 1.9 ghz ? 21 db gain at 1.9 ghz ? high isolation 32 db at 1.9 ghz ? single +3v supply ? unconditionally stable applications ? lo buffer and driver amplifier for cellular, cordless, special mobile radio, pcs, ism, wireless lan, dbs, tvro, and tv tuner input v d output & v d gnd1 gnd2
2 thermal resistance [2] : q jc = 170 c/w notes: 1. operation of this device above any one of these limits may cause permanent damage. 2. t c = 25 c (t c is defined to be the temperature at the package pins where contact is made to the circuit board) INA-34063 electrical specifications , t c = 25 c, z o = 50 w ,v d = 3 v symbol parameters and test conditions units min. typ. max. std. dev. [4] |s 21 | 2 gain in 50 w system f = 0.9 ghz db 20.1 f = 1.9 ghz 18.0 [3] 21.4 0.39 f = 2.4 ghz 20.6 nf 50 noise figure f = 1.9 ghz db 4.5 0.19 p 1db output power at 1 db gain compression f = 0.9 ghz dbm 7.8 f = 1.9 ghz 8.2 f = 2.4 ghz 6.5 ip 3 output third order intercept point f = 0.9 ghz dbm 19.4 f = 1.9 ghz 18.0 f = 2.4 ghz 15.6 vswr in input vswr f = 0.1 C 2.4 ghz 1.35:1 vswr out output vswr f = 0.1 C 2.4 ghz 1.10:1 i d device current ma 30 37 [3] 0.9 notes: 3. guaranteed specifications are 100% tested in production. 4. standard deviation number is based on measurement of a large number of parts from three non-consecutive wafer lots during the initial characterization of this product, and is intended to be used as an estimate for distribution of the typical specification. absolute maximum ratings absolute symbol parameter units maximum [1] v d device voltage, v 6.0 rf output to ground p in cw rf input power dbm +7.0 t j junction temperature c 150 t stg storage temperature c -65 to 150
3 INA-34063 typical performance, t c = 25 c, z o = 50 w , v d = 3 v 10 25 20 15 0 1.0 0.5 1.5 2.0 3.0 2.5 1.0 0.5 1.5 2.0 3.0 2.5 1.0 0.5 1.5 2.0 3.0 2.5 1.0 0.5 1.5 2.0 3.0 2.5 gain (db) frequency (ghz) figure 1. gain vs. frequency and voltage. noise figure (db) frequency (ghz) figure 2. noise figure vs. frequency and voltage. p 1 db (dbm) frequency (ghz) figure 3. output power for 1 db gain compression vs. frequency and voltage. gain (db) frequency (ghz) figure 4. gain vs. frequency and temperature. noise figure (db) frequency (ghz) figure 5. noise figure vs. frequency and temperature. figure 6. output power for 1 db gain compression vs. frequency and temperature. 2.7 v 3.0 v 3.3 v 10 25 0 1.0 0.5 1.5 2.0 3.0 2.5 0 -40 c +25 c +85 c 1.0 0.5 1.5 2.0 2.5 3 6 0 2.7 v 3.0 v 3.3 v 0 12 0 3.0 2.7 v 3.0 v 3.3 v p 1 db (dbm) frequency (ghz) -40 c +25 c +85 c vswr frequency (ghz) figure 7. input and output vswr vs. frequency. 0 3 vswr in vswr out i d (ma) v d (v) figure 8. supply current vs. voltage and temperature. 0 02 1345 4 4.5 3.5 5.5 5 4 5 3 6 20 30 10 40 2 7 50 0 -40 c +25 c +85 c -40 c +25 c +85 c figure 9. third order intercept point, ip 3 vs. frequency and temperature. ip 3 (dbm) frequency (ghz) 10 22 14 18 12 0 20 16 1 2 0.5 2.5 1.5 20 15 8 10 6 2 4 4 6 2 10 8 -40 c +25 c +85 c 0 12 0 1.0 0.5 1.5 2.0 3.0 2.5 1.0 0.5 1.5 2.0 3.0 2.5
4 INA-34063 typical scattering parameters [5] , t c = 25 c, z o = 50 w ,v d = 3.0 v freq. s 11 s 21 s 12 s 22 k ghz mag ang db mag ang db mag ang mag ang factor 0.1 0.14 2 19.3 9.23 -4 -28.0 0.040 1.65 0.049 -42 1.50 0.2 0.14 3 19.3 9.26 -9 -28.9 0.036 -1 0.085 -24 1.61 0.3 0.14 2 19.4 9.30 -13 -28.7 0.037 -5 0.070 -26 1.58 0.4 0.15 2 19.4 9.38 -17 -29.2 0.035 -10 0.089 -16 1.62 0.5 0.15 4 19.5 9.48 -22 -29.3 0.034 -8 0.077 -33 1.65 0.6 0.15 -1 19.6 9.58 -27 -29.1 0.035 -11 0.059 -38 1.61 0.7 0.16 -3 19.8 9.75 -31 -29.5 0.034 -14 0.069 -44 1.61 0.8 0.16 -5 19.9 9.93 -36 -29.9 0.032 -14 0.080 -56 1.67 0.9 0.17 -7 20.1 10.12 -41 -30.2 0.031 -15 0.087 -74 1.67 1.0 0.17 -10 20.3 10.31 -46 -30.2 0.031 -15 0.097 -90 1.65 1.1 0.18 -13 20.4 10.53 -52 -30.3 0.030 -16 0.104 -103 1.66 1.2 0.18 -16 20.6 10.75 -57 -30.6 0.030 -19 0.115 -111 1.62 1.3 0.18 -20 20.8 10.96 -63 -30.9 0.029 -20 0.136 -123 1.64 1.4 0.18 -23 21.0 11.16 -69 -31.2 0.027 -20 0.160 -131 1.70 1.5 0.18 -26 21.1 11.29 -76 -31.5 0.026 -21 0.190 -140 1.72 1.6 0.18 -32 21.1 11.39 -82 -31.6 0.026 -22 0.212 -154 1.70 1.7 0.18 -39 21.3 11.56 -89 -31.9 0.025 -25 0.217 -159 1.73 1.8 0.18 -45 21.3 11.68 -95 -32.3 0.024 -27 0.237 -166 1.76 1.9 0.17 -50 21.4 11.75 -103 -32.8 0.023 -29 0.256 -172 1.81 2.0 0.17 -55 21.4 11.76 -110 -33.1 0.022 -30 0.270 -178 1.87 2.1 0.18 -61 21.3 11.65 -118 -33.6 0.021 -34 0.284 178 1.94 2.2 0.18 -64 21.1 11.37 -125 -34.1 0.020 -36 0.303 172 2.04 2.3 0.18 -67 20.9 11.04 -132 -34.7 0.018 -39 0.318 166 2.28 2.4 0.19 -69 20.6 10.73 -140 -35.2 0.017 -43 0.326 160 2.44 2.5 0.20 -73 20.3 10.33 -147 -35.7 0.016 -48 0.326 156 2.66 2.6 0.20 -74 19.9 9.85 -154 -36.3 0.015 -54 0.330 152 2.95 2.7 0.20 -77 19.5 9.39 -161 -37.1 0.014 -63 0.331 147 3.29 2.8 0.21 -79 19.0 8.92 -167 -38.0 0.013 -73 0.331 142 3.69 2.9 0.21 -84 18.6 8.50 -173 -39.1 0.011 -83 0.325 138 4.57 3.0 0.22 -87 18.1 8.03 -180 -39.8 0.010 -96 0.314 134 5.32 3.1 0.22 -92 17.6 7.59 17 -40.8 0.009 -113 0.305 130 6.29 3.2 0.23 -96 17.1 7.19 169 -41.5 0.008 -130 0.293 126 7.48 3.3 0.25 -101 16.6 6.78 163 -41.6 0.008 -143 0.277 122 7.93 3.4 0.26 -106 16.1 6.39 158 -41.0 0.009 -153 0.262 119 7.51 3.5 0.27 -109 15.6 6.02 153 -39.5 0.011 -162 0.249 116 6.53 3.6 0.28 -112 15.1 5.69 148 -37.8 0.013 -172 0.234 112 5.86 3.7 0.30 -115 14.6 5.37 143 -36.6 0.015 -178 0.217 109 5.36 3.8 0.31 -118 14.1 5.07 139 -35.3 0.017 178 0.201 106 5.02 3.9 0.31 -120 13.6 4.80 134 -33.7 0.021 174 0.188 102 4.32 4.0 0.32 -122 13.2 4.55 130 -32.3 0.024 170 0.173 98 3.99 4.1 0.33 -125 12.7 4.32 126 -31.3 0.027 165 0.158 94 3.74 4.2 0.34 -128 12.2 4.09 122 -30.2 0.031 163 0.144 89 3.43 4.3 0.34 -131 11.8 3.89 118 -29.2 0.035 160 0.130 84 3.22 4.4 0.35 -135 11.4 3.70 114 -28.1 0.039 156 0.117 77 3.03 4.5 0.35 -138 10.9 3.52 110 -27.3 0.043 154 0.104 71 2.91 4.6 0.36 -142 10.5 3.35 106 -26.5 0.047 151 0.093 63 2.78 4.7 0.37 -146 10.1 3.19 103 -25.7 0.052 148 0.083 55 2.63 4.8 0.37 -149 9.6 3.04 99 -25.1 0.055 146 0.075 46 2.62 4.9 0.38 -152 9.3 2.90 96 -24.3 0.061 143 0.070 36 2.46 5.0 0.39 -156 8.9 2.77 93 -23.6 0.066 141 0.066 24 2.37 note: 5. reference plane per figure 15 in applications information section.
5 INA-34063 applications information introduction the INA-34063 is a +3 volt silicon rfic amplifier that is designed with a two stage internal network to provide a broadband gain and 50 w input and output impedance. with a p -1 db compressed output power of 8 dbm and noise figure of 4.5 db at 1900 mhz, the INA-34063 is well suited for amplifier applications in mobile communication. a feature of the INA-34063 is a positive gain slope over the 1C2 ghz range that is useful in many satellite-based tv and datacom systems. in addition to use in tv delivery systems, the INA-34063 will find many applications in battery operated wireless communication systems. operating details the INA-34063 is a voltage-biased device that operates from a +3 volt power supply with a typical current drain of 30 ma. all bias regulation circuitry is integrated into the rfic. figure 10 shows a typical imple- mentation of the INA-34063. the supply voltage for the INA-34063 must be applied to two terminals, the v d pin and the rf output pin. rf output rf input v d c bypass c out c block 34 rfc gnd2 gnd1 gnd1 figure 10. basic amplifier application. the v d connection to the ampli- fier is rf bypassed by placing a capacitor to ground near the v d pin of the amplifier package. the power supply connection to the rf output pin is achieved by means of a rf choke (inductor). the value of the rf choke must be large relative to 50 w in order to prevent loading of the rf output. the supply voltage end of the rf choke is bypassed to ground with a capacitor. if the physical layout permits, this can be the same bypass capacitor that is used at the v d terminal of the amplifier. blocking capacitors are normally placed in series with the rf input and the rf output to isolate the dc voltages on these pins from circuits adjacent to the amplifier. the values for the blocking and bypass capacitors are selected to provide a reactance at the lowest frequency of operation that is small relative to 50 w . example layout for 50 w output amplifier an example layout for an ampli- fier using the INA-34063 with 50 w input and 50 w output is shown in figure 11. rf output and v d gnd 1 rf input gnd 1 gnd 2 50 50 figure 11. rf layout. this example uses a microstripline design (solid groundplane on the backside of the circuit board). the circuit board material is 0.031-inch thick fr-4. plated through holes (vias) are used to bring the ground to the topside of the circuit where needed. the performance of INA-34063 is sensitive to ground path inductance. the two-stage design creates the possibility of a feedback loop being formed through the ground returns of the stages, gnd 1 and gnd 2. gnd 1 gnd 2 via figure 12. INA-34063 potential ground loop. gnd 1 gnd 2 via via figure 13. INA-34063 suggested layout. at least one ground via should be placed adjacent to each ground pin to assure good rf grounding. multiple vias are used to reduce the inductance of the path to ground and should be placed as close to the package terminals as practical. the effects of the potential ground loop shown in figure 12 may be observed as a peaking in the gain versus frequency response, an increase in input vswr, or even as return gain at the input of the INA-34063. figure 14 shows an assembled amplifier. the +3 volt supply is fed directly into the v d pin of the
6 INA-34063 and into the rf output pin through the rf choke (rfc). capacitor c3 provides rf bypass- ing for both the v d pin and the power supply end of the rfc. capacitor c4 is optional and may be used to add additional bypass- ing for the v d line. a well-by- passed v d line is especially necessary in cascades of ampli- fier stages to prevent oscillation that may occur as a result of rf feedback through the power supply lines. for this demonstration circuit, the value chosen for the rf choke was 120 nh (coilcraft 1008cs-221, toko ll2012-f or equivalent). all of the blocking and bypass capacitors are 100 pf. the gap in the output transmis- sion line was bridged using copper foil cut to size. these values provide excellent amplifier performance from under 50 mhz through 2.4 ghz. larger values for the choke and capacitors can be used to extend the lower end of the bandwidth. since the gain of the INA-34063 extends down to dc, the frequency response of the amplifier is limited only by the values of the capacitors and choke. a convenient method for making rf connection to the demonstra- tion board is to use a pcb mount- ing type of sma connector (johnson 142-0701-881, or equivalent). these connectors can be slipped over the edge of the pcb and the center conductor soldered to the input and output lines. the ground pins of the connectors can be soldered to the ground plane on the backside of board. pcb materials typical choices for pcb material for low cost wireless applications are fr-4 or g-10 with a thickness of 0.025 (0.635 mm) or 0.031inches (0.787 mm) a thick- ness of 0.062 inches (1.574 mm) is the maximum that is recom- mended for use with this particu- lar device. the use of a thicker board material increases the inductance of the plated through vias used for rf grounding and may deteriorate circuit perfor- mance. adequate grounding is needed not only to obtain maxi- mum amplifier performance but also to reduce any possibility of instability. phase reference planes the positions of the reference planes used to measure s-param- eters for this device are shown in figure 15. as seen in the illustra- tion, the reference planes are located at the point where the package leads contact the test circuit. reference planes test circuit figure 15. phase reference planes. sot-363 pcb layout the INA-34063 is packaged in the miniature sot-363 (sc-70) surface mount package. a pcb pad layout for the sot-363 package is shown in figure 16 (dimensions are in inches). this layout provides ample allowance for package placement by auto- mated assembly equipment without adding pad parasitics that could impair the high frequency performance of the INA-34063. the layout that is shown with a nominal sot-363 package foot- print superimposed on the pcb pads for reference. c2 rfc c1 c3 c4 v d ina-3xx63 demo board 32 figure 14. assembled amplifier.
7 0.026 0.075 0.016 0.035 figure 16. pcb pad layout for ina-32063 (dimensions in inches). statistical parameters several categories of parameters appear within this data sheet. parameters may be described with values that are either minimum or maximum, typical, or standard deviations. the values for parameters are based on compre- hensive product characterization data, in which automated mea- surements are made on a large number of parts taken from 3 non-consecutive process lots of semiconductor wafers. the data derived from product character- ization tends to be normally distributed, e.g., fits the standard bell curve. parameters considered to be the most important to system perfor- mance are bounded by minimum or maximum values. for the INA-34063, these parameters are: power gain (|s21| 2 ) and the device current (i d ). each of these guaranteed parameters is 100% tested. values for most of the parameters in the table of electrical specifications that are described by typical data are the mathematical mean ( m ), of the normal distribution taken from the characterization data. for parameters where measurements or mathematical averaging may not be practical, such as s-parameters or noise param- eters and the performance curves, the data represents a nominal part taken from the center of the characterization distribution. typical values are intended to be used as a basis for electrical design. to assist designers in optimizing not only the immediate circuit using the INA-34063, but to also optimize and evaluate trade-off that affect a complete wireless system, the standard deviation ( s ) is provided for many of the electrical specifications param- eters (at 25 c) in addition to the mean. the standard deviation is a measure of the variability about the mean. it will be recalled that a normal distribution is completely described by the mean and standard deviation. standard statistics tables or calculations provide the probabil- ity of a parameter falling between any two values, usually symmetri- cally located about the mean. referring to figure 17 for ex- ample, the probability of a parameter being between 1 s is 68.3%; between 2 s is 95.4%; and between 3 s is 99.7%. 68% 95% 99% parameter value mean ( ), typ -3 s -2 s -1 s +1 s +2 s +3 s figure 17. normal distribution. smt assembly reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., ir or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. components with a low mass, such as the sot-363 package, will reach solder reflow temperatures faster than those with a greater mass. the INA-34063 has been qualified to the time-temperature profile shown in figure 18. this profile is representative of an ir reflow type of surface mount assembly process. after ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. the preheat zones increase the temperature of the board and components to prevent thermal shock and begin evapo- rating solvents from the solder paste. the reflow zone briefly elevates the temperature suffi- ciently to produce a reflow of the solder. the rates of change of tempera- ture for the ramp-up and cool down zones are chosen to be low enough to not cause deformation of the board or damage to compo- nents due to thermal shock. these parameters are typical for a surface mount assembly
8 time (seconds) t max temperature ( c) 0 0 50 100 150 200 250 60 preheat zone cool down zone reflow zone 120 180 240 300 figure 18. surface mount assembly profile. process for the INA-34063. as a general guideline, the circuit board and components should only be exposed to the minimum temperatures and times neces- sary to achieve a uniform reflow of solder. for more information on mount- ing considerations for packaged microwave semiconductors please refer to agilent application note an-a006. electrostatic sensitivity rfics are electrostatic discharge (esd) sensitive devices. although the INA-34063 is robust in design, permanent damage may occur to these devices if they are sub- jected to high-energy electrostatic discharges. electrostatic charges as high as several thousand volts (which readily accumulate on the human body and on test equip- ment) can discharge without detection and may result in degradation in performance or failure. electronic devices may be subjected to esd damage in any of the following areas: ? storage & handling ? inspection & testing ? assembly ? in-circuit use the INA-34063 is an esd class 1 device. therefore, proper esd precautions are recommended when handling, inspecting, and assembling these devices to avoid damage. for more information on electro- static discharge and control refer to agilent application note an- a004r.
9 package dimensions outline 63 (sot-363/sc-70) INA-34063 part number ordering information part number devices per container container INA-34063-blk 100 tape strip in antistatic bag INA-34063-tr1 3,000 7" reel INA-34063-tr2 10,000 13" reel 2.20 (0.087) 2.00 (0.079) 1.35 (0.053) 1.15 (0.045) 1.30 (0.051) ref. 0.650 bsc (0.025) 2.20 (0.087) 1.80 (0.071) 0.10 (0.004) 0.00 (0.00) 0.25 (0.010) 0.15 (0.006) 1.00 (0.039) 0.80 (0.031) 0.20 (0.008) 0.10 (0.004) 0.30 (0.012) 0.10 (0.004) 0.30 ref. 10 0.425 (0.017) typ. dimensions are in millimeters (inches)
10 tape dimensions and product orientation for outline 63 p p 0 p 2 f w c d 1 d e a 0 8 max. t 1 (carrier tape thickness) t t (cover tape thickness) 5 max. b 0 k 0 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 2.24 0.10 2.34 0.10 1.22 0.10 4.00 0.10 1.00 + 0.25 0.088 0.004 0.092 0.004 0.048 0.004 0.157 0.004 0.039 + 0.010 cavity diameter pitch position d p 0 e 1.55 0.05 4.00 0.10 1.75 0.10 0.061 0.002 0.157 0.004 0.069 0.004 perforation width thickness w t 1 8.00 0.30 0.255 0.013 0.315 0.012 0.010 0.0005 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance width tape thickness c t t 5.4 0.10 0.062 0.001 0.205 0.004 0.0025 0.00004 cover tape 34 34
www.semiconductor.agilent.com data subject to change. copyright ? 1999 agilent technologies 5967-5768e (11/99)

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